About the Job

Alphachips is a design solution provider with over 24 years of experience delivering high-quality chip design services and supporting customers in bringing innovative semiconductor products to market.

We are looking for experienced PI (Physical Implementation) and PD (Physical Design) Engineers to join our engineering team and contribute to the implementation of advanced SoC designs.

In this role, you will work across key stages of the ASIC implementation flow, including synthesis, DFT, STA, low-power design, physical design, and sign-off, and collaborate with engineering teams to successfully deliver high-quality silicon designs.

1. PI (Physical Implementation) Engineer

Key Responsibilities

• DFT Implementation
• SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax) 
• BIST/BIRA Insertion & Simulation (Tessent MBIST / JTAG / IJTAG) 
• SDC Creation & Cleanup 
• Spyglass LINT/SDC/DFT Checks 
• Logic Synthesis (DC/DCT/DCG) 
• Equivalence Checking (Formality / Conformal) 
• LDRC - Logic Design Rule Check (Spyglass_LDRC) 
• STA (Static Timing Analysis) & Timing Closure (Prime_Time, Physical-aware ECO) 
• Low Power Design (UPF, Power Gating, Clock Gating, Multi-voltage domains) 
• Power Analysis (Vectored / Vectorless, PTPX) 
• Simulator & Debugger: VCS / NC-verilog / Verdi 

Qualifications & Core Competencies

• 3+ years of experience in ASIC Frontend/Physical Implementation
• Understanding of SoC/ASIC design flow 
• Practical experience with hierarchical implementation (SYN / DFT / STA / UPF) 
• Hands-on skills in EDA tools, logic synthesis, and low-power implementation 
• Preferred: Experience in Samsung 14nm or below process 

2. PD(Physical Design) Engineer

Key Responsibilities

• Full-chip Physical Design (Floorplan, P&R, CTS) for advanced SoCs
• Timing, Power, and Physical Verification closure (STA/IR/EM/DRC/LVS)
• Low power design implementation and verification (UPF/CPF)
• Design flow development using scripting (Python, TCL)
• Technical leadership and mentorship in complex design environments

Qualifications & Core Competencies

• 3+ years of experience in ASIC Backend/Physical Design
• Proficient in Synopsys (ICC2, Fusion Compiler, PrimeTime) or Cadence (Innovus, Tempus)
• Hands-on experience with advanced nodes (10nm or below preferred)
• Solid skills in Physical Design, STA, low power methodology, and scripting (Python/TCL/Perl)
• Preferred: Experience in large-scale SoC, strong communication and problem-solving skills

Location | 근무지

• HQ Office (Bundang-gu, Seongnam-si, Gyeonggi-do) | 본사 (경기도 성남시 분당구)

How to Apply | 지원방법

• Required Document | 필수 제출서류: 첨부된 당사 지정 이력서 양식

• Optional Documents | 선택 제출서류: 포트폴리오 등 직무 관련 추가 자료

• How to Apply | 지원방법: 아래 "Apply" 버튼을 통해 제출